1. Field of the Invention
The present invention relates to methods for forming semiconductor devices. More particularly, the present invention relates to methods for integrating nanotube memory cells in the semiconductor integrated circuit formation process.
2. Description of the Related Art
Designers and semiconductor device manufacturers constantly strive to develop smaller devices from wafers, recognizing that circuits with smaller features generally produce greater speeds and increased packing density, therefore increased net die per wafer (numbers of usable chips produced from a standard semiconductor wafer). These trends apply equally to memory devices. It is generally desirable for nonvolatile memory devices used in integrated circuits to have low cost, low power, high density, and high speed attributes. Conventional memory technology such as used in ROM are available at relatively low cost but can be programmed only once. DRAM memory devices rely on charged transistor gates but require separate circuitry to refresh the memory hundreds of times per second. Combining the advantages of each has been a goal of memory manufacturers. That is, a desirable memory device would provide access speeds equal to or greater than random-access memory (RAM) chips that are currently used for frequently accessed memory as well as the ability to store information even without power.
One promising technology uses carbon nanotubes to form a controllable switch. Carbon nanotubes are formed from a cylindrical array of carbon atoms whose diameter is only about 1 nm. Memory arrays using carbon nanotubes as the active conducting element in electromechanical switches have been proposed, for example, by Nantero, Ltd. of Woburn, Mass.
One integration process currently proposed requires the formation of an empty chamber to allow movement of a nanotube switch element. Unfortunately, formation of these chambers requires creating a pathway for removing a sacrificial material then filling this pathway without damaging either the nanotubes or metal electrodes.
Moreover, filling the chambers must be avoided during subsequent steps. Current methods either require precise process control or are unreliable. Moreover, the steps in the process flow should be compatible with the current CMOS manufacturing environment.
Accordingly, what is needed is an improved process for forming nanotube memory cells having greater compatibility with conventional CMOS flow steps. In particular, it is desirable to provide a simplified process flow for forming nanotube memory cells in which the memory cells are reliably formed.